D
flip-flop
The D flip-flop is the most common
flip-flop in use today. It is better known as delay flip-flop
The Q output always takes on the
state of the D input at the moment of a positive edge (or negative edge if the
clock input is active low). It is called the D flip-flop
for this reason, since the output takes the value of the D input or Data
input, and Delays it by one clock count. The D flip-flop can be
interpreted as a primitive memory cell, aero order hold, or delay line.
Whenever the clock pulses, the value of Qnext is D and Qprev
otherwise.
Truth table:
Clock
|
D
|
Q
|
Qprev
|
Rising
edge
|
0
|
0
|
X
|
Rising
edge
|
1
|
1
|
X
|
Non-Rising
|
X
|
Qprev
|
('X' denotes a Don’t care condition,
meaning the signal is irrelevant)
These flip-flops are very useful, as
they form the basis for shift registers, which are an essential part of many
electronic devices. The advantage of the D flip-flop over the D-type latch is
that it "captures" the signal at the moment the clock goes high, and
subsequent changes of the data line do not influence Q until the next rising
clock edge. An exception is that some flip-flops have a "reset"
signal input, which will reset Q (to zero), and may be either asynchronous or
synchronous with the clock.
The above circuit shifts the
contents of the register to the right, one bit position on each active
transition of the clock. The input X is shifted into the leftmost bit position.
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